88 English-speaking jobs in Cannes - Crasse

Manages and develops ETSI's website, ensuring a consistent look and feel across all pages. Develops and maintains web editing guidelines, manages the editorial calendar, and reviews content. Creates digital assets (text, images, videos) aligned with the marketing communication plan. Tracks website performance and proposes improvements. Promotes ETSI activities online and manages social media support.

Designs and scales evaluation systems to measure the performance and reliability of AI models. Builds human-in-the-loop and automated annotation pipelines for model assessment. Defines and implements continuous evaluation workflows to monitor model behavior. Collaborates cross-functionally to establish best practices for responsible AI.

Applications Engineer will support partners through technical challenges related to Arm CPU IP and Subsystem products. Responsibilities include analyzing requests, providing solutions, developing training courses, and collaborating with engineering teams. Requires a Bachelor's Degree or higher in Electronic Engineering, experience in the ASIC industry, and strong understanding of HDLs, CPU architecture, and SoC design principles.

Senior IP Qualification Engineer will verify Third-Party IPs (standard-cells, memories, interfaces) before embedding in Arm SoCs. Responsibilities include ensuring RTL design and EDA models align with Arm SoC design flow, verifying methodology, and analyzing deviations. Requires 5+ years experience in RTL, low-power verification, scripting, and System Verilog.

Intern will investigate architecture enhancements for the Scalable Matrix Extension (SME), supporting AI, Machine Learning, Computer Vision, telecommunications, and HPC applications. Responsibilities include analyzing applications and prototyping innovative instructions.

Senior Verification Engineer to verify RTL implementing ARM SoC features, ensuring functionality meets architectural requirements. Collaborate with RTL team, develop verification environments, and mentor other engineers. Requires 5+ years of IP/SOC verification experience, proficiency in SystemVerilog, UVM Methodology, and SoC Verification using C Testcases. Experience with ARM-based designs and scripting languages is essential.

Wallester seeks a Partnership Manager to oversee relationships with fintech and payment associations. Responsibilities include developing engagement strategies, coordinating events, managing projects, and representing the organization at industry gatherings. Requires 5-10 years of experience in association management, a master's degree, and strong communication and project management skills.

CPU Verification Intern will participate in verifying Arm Cortex IPs using various methodologies, tools, and programming languages. Develop scripts, tools, models, and testbenches using languages like UVM, SystemVerilog, C, C++, and Python.

Intern will investigate architecture enhancements for the Scalable Matrix Extension (SME), supporting AI, Machine Learning, Computer Vision, telecommunication, and HPC applications. Responsibilities include analyzing applications and prototyping innovative instructions.

System, Network Security Administration apprenticeship supporting IT infrastructure management, including workstations, servers, networks, and internal services. Responsibilities include website administration, software testing, and customer support.

Embedded Software Engineer will design, develop, and debug C/C++ software for embedded systems in real-time environments. Collaborate with multidisciplinary teams to integrate and validate software solutions across industries such as aerospace, automotive, and telecommunications.

DevOps Engineer to support ongoing projects focused on Cloud migration, web applications, and Security improvements in a SAFe environment. Tasks include automating CI/CD processes, system supervision, and environment security. Expertise in Jenkins, Docker, Kubernetes, Grafana, Prometheus, and Azure Cloud is required.

Java Springboot Developer will implement and develop software, integrate solutions, and participate in digital transformation projects. Requires a Bac + 5 in computer development, 4 years of experience, Java, Spring, and Springboot mastery, autonomy, strong communication skills, and conversational English.

IT Support Technician provides first and second-level support to end users, troubleshooting hardware and software issues. Responsibilities include assembly, installation, and monitoring of IT equipment, on-site and remote intervention for technical issues, and ensuring network and data security.

Provides regulatory strategy and direction for AI software programs, supporting global registration planning, submissions, and post-market compliance. Develops regulatory strategies to optimize submission pathways, considering regulatory requirements, product claims, and country dependencies. Assesses changes to existing products and determines the need for new licenses or registrations.

System, Network Security Administration apprenticeship supporting IT infrastructure management, including workstations, servers, networks, and internal services. Responsibilities include website administration, software testing, and customer support.

As a Graduate Verification Engineer, you will join a team responsible for guaranteeing the correct functioning of IP, focusing on its accurate functional behavior. You will understand the specification of the target IP, define and document the verification environment, build and maintain the testbench, and run tests to stress the design.

Senior QA Automation Test Engineer will design, implement, and maintain automated test strategies using Selenium & Robot Framework.

Momji seeks a part-time English nanny for 4 hours per week in ST LAURENT DU VAR, starting July 15, 2026. Duties include after-school and daycare pick-ups, homework help, snack time, assisting with hygiene, and park visits. Previous experience with children is required. EU citizenship or a work visa is necessary.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.